\doxysection{DMA\+\_\+\+Init\+Type\+Def Struct Reference}
\hypertarget{struct_d_m_a___init_type_def}{}\label{struct_d_m_a___init_type_def}\index{DMA\_InitTypeDef@{DMA\_InitTypeDef}}


DMA Configuration Structure definition.  




{\ttfamily \#include $<$stm32h7xx\+\_\+hal\+\_\+dma.\+h$>$}

\doxysubsubsection*{Public Attributes}
\begin{DoxyCompactItemize}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_d_m_a___init_type_def_a74997b2fac5607fafbb958d4311b9017}{Request}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_d_m_a___init_type_def_a0145b5d0e074fa8e2e185ecf2c4a15ca}{Direction}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_d_m_a___init_type_def_a46811eb656170cb5c542054d1a41db3a}{Periph\+Inc}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_d_m_a___init_type_def_a49b187ba5ab8ba4354e02837e8b99414}{Mem\+Inc}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_d_m_a___init_type_def_a10a4a549953efa20c235dcbb381b6f0b}{Periph\+Data\+Alignment}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_d_m_a___init_type_def_a7784efedc4a61325fa7364fcace10136}{Mem\+Data\+Alignment}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_d_m_a___init_type_def_adbbca090b53d32ac93cc7359b7994db2}{Mode}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_d_m_a___init_type_def_af110cc02c840207930e3c0e5de5d7dc4}{Priority}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_d_m_a___init_type_def_acda0396cf55baab166f51b1ea1deed0d}{FIFOMode}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_d_m_a___init_type_def_a2f994cc2979b82cd215e9f38edbbc6ed}{FIFOThreshold}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_d_m_a___init_type_def_ad5e266a0b90f58365e21c349654bc68d}{Mem\+Burst}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_d_m_a___init_type_def_a3fbfe4dd664e24845dc75f5c8f43b5a3}{Periph\+Burst}}
\end{DoxyCompactItemize}


\doxysubsection{Detailed Description}
DMA Configuration Structure definition. 

\label{doc-variable-members}
\Hypertarget{struct_d_m_a___init_type_def_doc-variable-members}
\doxysubsection{Member Data Documentation}
\Hypertarget{struct_d_m_a___init_type_def_a0145b5d0e074fa8e2e185ecf2c4a15ca}\index{DMA\_InitTypeDef@{DMA\_InitTypeDef}!Direction@{Direction}}
\index{Direction@{Direction}!DMA\_InitTypeDef@{DMA\_InitTypeDef}}
\doxysubsubsection{\texorpdfstring{Direction}{Direction}}
{\footnotesize\ttfamily \label{struct_d_m_a___init_type_def_a0145b5d0e074fa8e2e185ecf2c4a15ca} 
uint32\+\_\+t DMA\+\_\+\+Init\+Type\+Def\+::\+Direction}

Specifies if the data will be transferred from memory to peripheral, from memory to memory or from peripheral to memory. This parameter can be a value of \doxylink{group___d_m_a___data__transfer__direction}{DMA Data transfer direction} \Hypertarget{struct_d_m_a___init_type_def_acda0396cf55baab166f51b1ea1deed0d}\index{DMA\_InitTypeDef@{DMA\_InitTypeDef}!FIFOMode@{FIFOMode}}
\index{FIFOMode@{FIFOMode}!DMA\_InitTypeDef@{DMA\_InitTypeDef}}
\doxysubsubsection{\texorpdfstring{FIFOMode}{FIFOMode}}
{\footnotesize\ttfamily \label{struct_d_m_a___init_type_def_acda0396cf55baab166f51b1ea1deed0d} 
uint32\+\_\+t DMA\+\_\+\+Init\+Type\+Def\+::\+FIFOMode}

Specifies if the FIFO mode or Direct mode will be used for the specified stream. This parameter can be a value of \doxylink{group___d_m_a___f_i_f_o__direct__mode}{DMA FIFO direct mode} \begin{DoxyNote}{Note}
The Direct mode (FIFO mode disabled) cannot be used if the memory-\/to-\/memory data transfer is configured on the selected stream 
\end{DoxyNote}
\Hypertarget{struct_d_m_a___init_type_def_a2f994cc2979b82cd215e9f38edbbc6ed}\index{DMA\_InitTypeDef@{DMA\_InitTypeDef}!FIFOThreshold@{FIFOThreshold}}
\index{FIFOThreshold@{FIFOThreshold}!DMA\_InitTypeDef@{DMA\_InitTypeDef}}
\doxysubsubsection{\texorpdfstring{FIFOThreshold}{FIFOThreshold}}
{\footnotesize\ttfamily \label{struct_d_m_a___init_type_def_a2f994cc2979b82cd215e9f38edbbc6ed} 
uint32\+\_\+t DMA\+\_\+\+Init\+Type\+Def\+::\+FIFOThreshold}

Specifies the FIFO threshold level. This parameter can be a value of \doxylink{group___d_m_a___f_i_f_o__threshold__level}{DMA FIFO threshold level} \Hypertarget{struct_d_m_a___init_type_def_ad5e266a0b90f58365e21c349654bc68d}\index{DMA\_InitTypeDef@{DMA\_InitTypeDef}!MemBurst@{MemBurst}}
\index{MemBurst@{MemBurst}!DMA\_InitTypeDef@{DMA\_InitTypeDef}}
\doxysubsubsection{\texorpdfstring{MemBurst}{MemBurst}}
{\footnotesize\ttfamily \label{struct_d_m_a___init_type_def_ad5e266a0b90f58365e21c349654bc68d} 
uint32\+\_\+t DMA\+\_\+\+Init\+Type\+Def\+::\+Mem\+Burst}

Specifies the Burst transfer configuration for the memory transfers. It specifies the amount of data to be transferred in a single non interruptible transaction. This parameter can be a value of \doxylink{group___d_m_a___memory__burst}{DMA Memory burst} \begin{DoxyNote}{Note}
The burst mode is possible only if the address Increment mode is enabled. 
\end{DoxyNote}
\Hypertarget{struct_d_m_a___init_type_def_a7784efedc4a61325fa7364fcace10136}\index{DMA\_InitTypeDef@{DMA\_InitTypeDef}!MemDataAlignment@{MemDataAlignment}}
\index{MemDataAlignment@{MemDataAlignment}!DMA\_InitTypeDef@{DMA\_InitTypeDef}}
\doxysubsubsection{\texorpdfstring{MemDataAlignment}{MemDataAlignment}}
{\footnotesize\ttfamily \label{struct_d_m_a___init_type_def_a7784efedc4a61325fa7364fcace10136} 
uint32\+\_\+t DMA\+\_\+\+Init\+Type\+Def\+::\+Mem\+Data\+Alignment}

Specifies the Memory data width. This parameter can be a value of \doxylink{group___d_m_a___memory__data__size}{DMA Memory data size} \Hypertarget{struct_d_m_a___init_type_def_a49b187ba5ab8ba4354e02837e8b99414}\index{DMA\_InitTypeDef@{DMA\_InitTypeDef}!MemInc@{MemInc}}
\index{MemInc@{MemInc}!DMA\_InitTypeDef@{DMA\_InitTypeDef}}
\doxysubsubsection{\texorpdfstring{MemInc}{MemInc}}
{\footnotesize\ttfamily \label{struct_d_m_a___init_type_def_a49b187ba5ab8ba4354e02837e8b99414} 
uint32\+\_\+t DMA\+\_\+\+Init\+Type\+Def\+::\+Mem\+Inc}

Specifies whether the memory address register should be incremented or not. This parameter can be a value of \doxylink{group___d_m_a___memory__incremented__mode}{DMA Memory incremented mode} \Hypertarget{struct_d_m_a___init_type_def_adbbca090b53d32ac93cc7359b7994db2}\index{DMA\_InitTypeDef@{DMA\_InitTypeDef}!Mode@{Mode}}
\index{Mode@{Mode}!DMA\_InitTypeDef@{DMA\_InitTypeDef}}
\doxysubsubsection{\texorpdfstring{Mode}{Mode}}
{\footnotesize\ttfamily \label{struct_d_m_a___init_type_def_adbbca090b53d32ac93cc7359b7994db2} 
uint32\+\_\+t DMA\+\_\+\+Init\+Type\+Def\+::\+Mode}

Specifies the operation mode of the DMAy Streamx. This parameter can be a value of \doxylink{group___d_m_a__mode}{DMA mode} \begin{DoxyNote}{Note}
The circular buffer mode cannot be used if the memory-\/to-\/memory data transfer is configured on the selected Stream 
\end{DoxyNote}
\Hypertarget{struct_d_m_a___init_type_def_a3fbfe4dd664e24845dc75f5c8f43b5a3}\index{DMA\_InitTypeDef@{DMA\_InitTypeDef}!PeriphBurst@{PeriphBurst}}
\index{PeriphBurst@{PeriphBurst}!DMA\_InitTypeDef@{DMA\_InitTypeDef}}
\doxysubsubsection{\texorpdfstring{PeriphBurst}{PeriphBurst}}
{\footnotesize\ttfamily \label{struct_d_m_a___init_type_def_a3fbfe4dd664e24845dc75f5c8f43b5a3} 
uint32\+\_\+t DMA\+\_\+\+Init\+Type\+Def\+::\+Periph\+Burst}

Specifies the Burst transfer configuration for the peripheral transfers. It specifies the amount of data to be transferred in a single non interruptible transaction. This parameter can be a value of \doxylink{group___d_m_a___peripheral__burst}{DMA Peripheral burst} \begin{DoxyNote}{Note}
The burst mode is possible only if the address Increment mode is enabled. 
\end{DoxyNote}
\Hypertarget{struct_d_m_a___init_type_def_a10a4a549953efa20c235dcbb381b6f0b}\index{DMA\_InitTypeDef@{DMA\_InitTypeDef}!PeriphDataAlignment@{PeriphDataAlignment}}
\index{PeriphDataAlignment@{PeriphDataAlignment}!DMA\_InitTypeDef@{DMA\_InitTypeDef}}
\doxysubsubsection{\texorpdfstring{PeriphDataAlignment}{PeriphDataAlignment}}
{\footnotesize\ttfamily \label{struct_d_m_a___init_type_def_a10a4a549953efa20c235dcbb381b6f0b} 
uint32\+\_\+t DMA\+\_\+\+Init\+Type\+Def\+::\+Periph\+Data\+Alignment}

Specifies the Peripheral data width. This parameter can be a value of \doxylink{group___d_m_a___peripheral__data__size}{DMA Peripheral data size} \Hypertarget{struct_d_m_a___init_type_def_a46811eb656170cb5c542054d1a41db3a}\index{DMA\_InitTypeDef@{DMA\_InitTypeDef}!PeriphInc@{PeriphInc}}
\index{PeriphInc@{PeriphInc}!DMA\_InitTypeDef@{DMA\_InitTypeDef}}
\doxysubsubsection{\texorpdfstring{PeriphInc}{PeriphInc}}
{\footnotesize\ttfamily \label{struct_d_m_a___init_type_def_a46811eb656170cb5c542054d1a41db3a} 
uint32\+\_\+t DMA\+\_\+\+Init\+Type\+Def\+::\+Periph\+Inc}

Specifies whether the Peripheral address register should be incremented or not. This parameter can be a value of \doxylink{group___d_m_a___peripheral__incremented__mode}{DMA Peripheral incremented mode} \Hypertarget{struct_d_m_a___init_type_def_af110cc02c840207930e3c0e5de5d7dc4}\index{DMA\_InitTypeDef@{DMA\_InitTypeDef}!Priority@{Priority}}
\index{Priority@{Priority}!DMA\_InitTypeDef@{DMA\_InitTypeDef}}
\doxysubsubsection{\texorpdfstring{Priority}{Priority}}
{\footnotesize\ttfamily \label{struct_d_m_a___init_type_def_af110cc02c840207930e3c0e5de5d7dc4} 
uint32\+\_\+t DMA\+\_\+\+Init\+Type\+Def\+::\+Priority}

Specifies the software priority for the DMAy Streamx. This parameter can be a value of \doxylink{group___d_m_a___priority__level}{DMA Priority level} \Hypertarget{struct_d_m_a___init_type_def_a74997b2fac5607fafbb958d4311b9017}\index{DMA\_InitTypeDef@{DMA\_InitTypeDef}!Request@{Request}}
\index{Request@{Request}!DMA\_InitTypeDef@{DMA\_InitTypeDef}}
\doxysubsubsection{\texorpdfstring{Request}{Request}}
{\footnotesize\ttfamily \label{struct_d_m_a___init_type_def_a74997b2fac5607fafbb958d4311b9017} 
uint32\+\_\+t DMA\+\_\+\+Init\+Type\+Def\+::\+Request}

Specifies the request selected for the specified stream. This parameter can be a value of \doxylink{group___d_m_a___request__selection}{DMA Request selection} 

The documentation for this struct was generated from the following file\+:\begin{DoxyCompactItemize}
\item 
C\+:/\+Users/\+ASUS/\+Desktop/dm-\/ctrl\+H7-\/balance-\/9025test/\+Drivers/\+STM32\+H7xx\+\_\+\+HAL\+\_\+\+Driver/\+Inc/\mbox{\hyperlink{stm32h7xx__hal__dma_8h}{stm32h7xx\+\_\+hal\+\_\+dma.\+h}}\end{DoxyCompactItemize}
